1. Field of the Invention
The present invention relates to a semiconductor memory device, particularly to an interconnection structure for reducing the resistance of interconnection lines arranged on a memory mat without increasing a memory mat area. The present invention more particularly relates to an interconnection structure for decreasing the resistance of interconnection lines located at the same layer as that of an interconnection line transmitting a memory cell selection signal.
2. Description of the Background Art
FIG. 17 schematically shows an entire structure of a conventional semiconductor memory device. In FIG. 17, a memory mat 1 having a plurality of memory cells MCs arranged in rows and columns is divided into a plurality of memory blocks MB#0-MB#n in a row direction. In each of memory blocks MB#0-MBn, a plurality of sub word lines SWLs placed corresponding to respective rows of memory cells MCs and having memory cells MCs of corresponding rows connected thereto, and a bit line pair BLP placed corresponding to each column of memory cells and having corresponding memory cells connected thereto are provided. FIG. 17 illustrates representatively one sub word line SWL, one bit line pair BLP, and a memory cell MC arranged corresponding to a crossing of sub word line SWL and bit line pair BLP.
A main word line MWL extending in the row direction is commonly provided to memory blocks MB#0-MB#n. Main word line MWL is arranged corresponding to a prescribed number of sub word lines in each of memory blocks MB#0-MB#, with the prescribed number being one or more. A sub word line driver SWD is placed corresponding to each sub word line SWL. Each sub word line driver SWD drives a corresponding sub word line SWL into a selected state according to at least a signal potential on a corresponding main word line MWL. If main word line MWL is arranged corresponding to each row of memory blocks MB#0-MB#n, sub word line driver SWD drives a corresponding sub word line SWL into a selected state according to a signal potential on the corresponding main word line MWL. If main word line MWL is arranged corresponding to memory cells of a plurality of rows in memory mat 1, sub word line driver SWD drives a corresponding sub word line SWL into a selected state according to a signal potential on the corresponding main word line MWL and a row address predecode signal (as discussed below).
The semiconductor memory device further includes a row selection drive circuit 2 driving main word line MWL placed corresponding to an addressed row into a selected state according to an address signal (not shown), a bit line equalize circuit 3 setting bit line pair BLP at a prescribed voltage in a standby state, a sense amplifier circuit 4 including a sense amplifier provided corresponding to each bit line pair BLP and differentially amplifying potential on the corresponding bit line pair BLP in an activated state, and a column selection circuit 5 selecting a bit line pair placed corresponding to an addressed column according to a column address signal (not shown). In a standby state, main word line MWL is in a non-selected state, and sub word lines SWLs in each of memory blocks MB#0-MB#n are also in a non-selected state. Bit line pair BLP is set (precharged and equalized) at a level of a prescribed voltage (an intermediate voltage between power supply voltage Vcc and ground voltage Vss) by bit line equalize circuit 3 .
When a memory cell selection cycle (active cycle) is started, row selection drive circuit 2 first drives main word line MWL corresponding to an addressed row into a selected state. Sub word line driver SWD drives a corresponding sub word line SWL into a selected state according to at least a signal potential on main word line MWL when the corresponding sub word line SWL corresponds to the addressed row. In each of memory blocks MB#0-MB#n, sub word line SWL placed corresponding to the addressed row is driven into a selected state. Accordingly, data stored in memory cell MC is transmitted onto bit line pair BLP.
Sense amplifier circuit 4 is then activated, data of memory cell MC read onto bit line pair BLP is sensed, amplified and latched. Data is written into or read from bit line pair BLP that corresponds to a column selected by column selection circuit 5.
Word lines arranged corresponding to memory cell rows each have a hierarchical structure formed of main word line MWL commonly provided to a plurality of memory blocks MB#0-MB#n, and sub word line SWL to which memory cells MCs are connected in each of memory blocks MB#0-MB#n. It is possible to transmit a row select drive signal fiom row selection drive circuit 2 to the end of main word line MWL at a high speed since no memory cell MC is connected to main word line MWL. The number of memory cells MCs connected to sub word line SWL is small and accordingly the parasitic capacitance of sub word line is small. Therefore, the hierarchical structure of word lines formed of the main word lines and sub word lines allows a memory cell row to be driven into a selected state at a high speed even if the storage capacity of the semiconductor memory device is increased and the number of memory cells of one row increases.
FIG. 18 shows one example of a structure of sub word line driver SWD illustrated in FIG. 17. FIG. 18 shows sub word line drivers provided to a memory block MB#i (i=0-n). One main word line MWL is arranged corresponding to sub word lines SWLa-SWLd placed corresponding to 4 rows of memory cells in memory block MB#i. Sub word line drivers SWDa-SWDd are arranged corresponding to respective sub word lines SWLa-SWLd.
Sub word line drivers SWDa-SWDd are respectively enabled when a signal potential on main word line MWL is at a logical high or H level indicating a selected state, and drive corresponding sub word lines SWLa-SWLd into a selected state respectively according to row predecode signals Ra-Rd. One of row predecode signals Ra-Rd is driven into a selected state to designate one of sub word lines SWLa-SWLd.
The arrangement shown in FIG. 18 allows one main word line MWL to be placed corresponding to memory cells of 4 rows to relax the pitch condition of main word lines MWLs. Consequently, main word line MWL can be arranged with a sufficient margin.
As an alternative to the structure shown in FIG. 18, decoders respectively enabled in response to a signal potential on main word line MWL to transmit row predecode signals Ra-Rd to corresponding sub word lines SWLa-SWLd may replace sub word line drivers SWDa-SWDd.
FIG. 19A schematically shows a structure of one memory block of the semiconductor memory device illustrated in FIG. 17. FIG. 19A shows a structure of a portion related to memory cells MCs arranged in two columns.
In FIG. 19A, memory block MB#i includes a plurality of memory cells MCs arranged in rows and columns, sub word lines SWLa, SWLB, . . . arranged corresponding to respective memory cell rows and having memory cells MCs of corresponding rows connected thereto, and a plurality of bit line pairs BLPa . . . BLPm arranged corresponding to respective memory cell columns and having memory cells of corresponding columns connected thereto. Bit line pair BLPa includes bit lines BLa and /BLa, and bit line pair BLPm includes bit lines BLm and /BLm. Memory cells MCs are arranged corresponding to crossings of bit line pairs BLPa . . . BPLm and sub word lines SWLa, SWLb, . . . FIG. 19A illustrates memory cells MCs arranged corresponding to respective crossings of sub word line SWLa and bit lines BLa and BLm, and memory cells MCs arranged corresponding to crossings of sub word line SWLb and bit lines /BLa and /BLm respectively.
Memory cell MC includes a memory capacitor MQ storing information, and an access transistor MT responsive to a signal potential on a corresponding sub word line SWL (SWLa or SWLb) to become conductive to connect memory capacitor MQ to a corresponding bit line BL (BLa, BLm) or /BL (/BLa, /BLm).
Memory capacitor MQ accumulates charge according to storage data on a storage node SN connected to access transistor MT, and receives a constant cell plate voltage Vcp at its cell plate electrode.
Bit line equalize circuit 3 includes bit line equalize/precharge circuits 3a . . . 3m provided corresponding to respective bit line pairs BLPa . . . BLPm. Bit line equalize/precharge circuits 3a-3m each have the same structure, and FIG. 19A representatively shows a specific structure of bit line equalize/precharge circuit 3a provided to bit line pair BLPa. Bit line equalize/precharge circuit 3a includes an n channel MOS transistor Q1 responsive to a bit line equalize instruction signal .phi.BLEQ to electrically short-circuit bit lines BLa and /BLa, and n channel MOS transistors Q2 and Q3 responsive to activation of bit line equalize instruction signal .phi.BLEQ to become conductive to transmit a prescribed precharge voltage Vb1 onto bit lines BLa and /BLa.
Sense amplifier circuit 4 includes sense amplifiers (Sas)4a . . . 4m provided corresponding to respective bit line pairs BLPa . . . BLPm, activated in response to activation of a sense amplifier activation signal .phi.SA, differentially amplifying and latching signal potential on bit line pairs BLPa . . . BLPm. Sense amplifiers (SAs) 4a-4m each include cross-coupled p channel MOS transistors and cross-coupled n channel MOS transistors.
Column selection circuit 5 includes IO gates 5a . . . 5m arranged corresponding to respective bit line pairs BLPa . . . BLPm, and rendered conductive in response to column selection signals YSa . . . Ysm to connect corresponding bit line pairs BLPa . . . BLPm to an internal data bus I/O. Referring now to FIG. 19B, an operation of the semiconductor memory device shown in FIG. 19A is described.
In a standby state, an array activation signal ACT is at a logical low or L level, and bit line equalize instruction signal .phi.BLEQ is at H level. In this state, bit line equalize/precharge circuits 3a-3m are in an active state, precharge and equalize bit line pairs BLPa-BLPm to the level of precharge voltage Vb1. Sub word line SWL (SWLa, SWLb, . . . ) is set at the L level of a non-selected state, and sense amplifier activation signal .phi.SA is also at the L level of a non-selected state. Array activation signal ACT is a signal which is internally activated when a memory cell row selection instruction signal is externally supplied, and corresponds to an internal row address strobe signal in a standard DRAM (Dynamic Random Access Memory).
The sense amplifier activation signal includes a signal activating an N sense amplifier section formed of n channel MOS transistors and a signal activating a P sense amplifier section formed of p channel MOS transistors respectively. FIG. 19B collectively shows them as one sense amplifier activation signal .phi.SA.
When the array activation instruction signal (external row address strobe signal or an active command) driving a memory cell row into a selected state is supplied, array activation signal ACT is set into an active state, bit line equalize instruction signal .phi.BLEQ accordingly falls to L level, bit line equalize/precharge circuits 3a-3m are set into an inactive state, and accordingly an equalize/precharge operation for bit line pairs BLPa-BLPm is completed. In this state, bit line pairs BLPa-BLPm are brought into the floating state at precharge voltage Vb1.
The potential on sub word line SWL placed corresponding to an addressed row then rises and data stored in memory cell MC connected to the selected sub word line SWL is transmitted to a corresponding bit line. FIG. 19B representatively illustrates bit lines BL and /BL and illustrates a signal waveform of the bit lines when storage data of the H level is read. Bit lines BL and /BL form a pair to be placed. When memory cell data is read onto one of bit lines BL and /BL, the other bit line keeps the level of precharge voltage Vb1.
When the potential difference between bit lines BL and /BL becomes sufficiently large, sense amplifier activation signal .phi.SA is activated and sense amplifiers 4a-4m are activated to differentially amplify memory cell data read onto bit line pairs BLPa-BLPm respectively. Accordingly, the potential on bit line pairs BLPa-BLPm is set at the levels of power supply voltage Vcc and the ground voltage according to the read data.
After the sense amplifier operation is completed, data is written into or read from a selected column via IO gates 5a-5m shown in FIG. 19A according to column selection signals YSa-YSm.
In the hierarchical word line structure, a row selection signal is transmitted through the main word line to transfer the row selection signal to the end of the memory mat at a high speed, in order to drive word lines into a selected state at a high speed. However, when a word line (including both of the main word line and the sub word line) is driven into a selected state, the signal potential on sub word line SWL cannot be raised before bit line equalize instruction signal .phi.BLEQ is driven into a non-selected state. When the potential on sub word line SWL increases during activation of bit line equalize/precharge circuits 3a-3m , data in a selected memory cell is destructed In order to drive the word lines into a selected state at a high speed, bit line equalize instruction signal .phi.BLEQ should be driven into a non-selected state as soon as possible.
In addition, after a memory cycle is completed and array activation signal ACT is in an inactive state, bit line equalize instruction signal .phi.BLEQ should be driven into an active state at a high speed. The reason is that if it takes much time to equalize the bit lines, the RAS precharge period increases and the word lines cannot be successively driven into a selected state at a high speed.
To a signal line transmitting bit line equalize instruction signal .phi.BLEQ, the gates of transistors included in the bit line equalize/precharge circuits provided to respective bit line pairs are connected, and accordingly a large gate capacitance is connected thereto. In order to drive the large parasitic capacitance at a high speed, the signal line transmitting bit line equalize instruction signal .phi.BLEQ is formed of, for example, a first level aluminum interconnection layer having a low resistance. The RC delay is thus reduced to activate/inactivate the bit line equalize/precharge circuits at a high speed.
FIG. 20 schematically shows a layout of interconnection lines of the conventional semiconductor memory device. Referring to FIG. 20, interconnection lines 10 of the first level aluminum interconnection layer constituting main word lines MWLs and extending in the row direction are arranged in memory mat. The first level aluminum interconnection lines 10 have the same width L and the same space (interval) S therebetween to make the RC delay in all main word lines MWLs equal. Conductive interconnection lines 10 are extended in the row direction in a straight form for transmitting signals at a high speed with a minimum interconnection length.
Between a sense amplifier arranging region 11 and memory mat 1, a conductive interconnection line 12 formed of the first level aluminum interconnection line for transmitting cell plate voltage Vcp, and a conductive interconnection line 13 for transmitting bit line equalize instruction signal .phi.BLEQ are arranged to extend in the row direction. Conductive interconnection line 12 transmitting cell plate voltage Vcp is electrically connected to a cell plate node at a lower layer in an appropriate region. Conductive interconnection line 13 transmitting bit line equalize instruction signal .phi.BLEQ should have a width as large as possible in order to transmit bit line equalize instruction signal .phi.BLEQ at a high speed.
As shown in FIG. 21 illustrating a cross sectional structure along line 20A--20A of FIG. 20, interconnection line 10 constituting main word line MWL, conductive interconnection line 12 transmitting cell plate voltage Vcp, and conductive interconnection line 13 transmitting bit line equalize instruction signal .phi.BLEQ are all formed at the same first level aluminum interconnection layer (1Al). Therefore, the width of conductive interconnection line 13 transmitting bit line equalize instruction signal .phi.BLEQ cannot be increased without affecting the layout of sense amplifier arranging region 11 since the minimum space between those interconnection lines is determined in view of an inter-line capacitance and the like. If the width of conductive interconnection line 13 is increased to reduce the resistance thereof, the layout of the sense amplifier arranging region 11 is affected and equivalently conductive interconnection line 13 and sense amplifier arranging region 11 occupy a larger area. In particular, if the memory mat is divided into a plurality of row blocks in the column direction and the sense amplifiers are arranged between row blocks adjacent to each other, the equivalently increased area of the sense amplifier arranging region increases the memory mat area and accordingly the chip size.
Sense amplifiers placed in the sense amplifier arranging region are provided to respective bit line pairs and have to drive the bit line pairs BLPa-BLPm at high speed.
FIG. 22 illustrates one example of a structure of a sense amplifier SA included in the sense amplifier circuit. Referring to FIG. 22, sense amplifier SA includes p channel MOS transistors PQa and PQb having the gates and drains cross-coupled to each other, a p channel MOS transistor PQc rendered conductive in response to activation (L level) of a P sense activation signal .phi.SP and transmitting power supply voltage Vcc on a sense power supply line 14 to the sources of p channel MOS transistors PQa and PQb, n channel MOS transistors NQa and NQb having the gates and drains cross-coupled to each other, and an n channel MOS transistor NQc rendered conductive in response to activation (H level) of an N sense activation signal .phi.SN, and transmitting ground voltage Vss on a sense ground line 15 to the sources of MOS transistors NQa and NQb.
MOS transistors PQa and PQb have drains respectively connected to bit lines BL and /BL, and MOS transistors NQa and NQb have drains respectively connected to bit lines BL and /BL.
In the structure of sense amplifier SA shown in FIG. 22, when MOS transistor PQc is activated, current is supplied from sense power supply line 14 to one of bit lines BL and /BL at a higher potential by MOS transistors PQa and PQb to drive the bit line at the higher potential to the level of power supply voltage Vcc. One of bit lines BL and /BL at a lower potential is driven to the level of ground voltage Vss on sense ground line 15 by MOS transistors NQa-NQc.
Sense power supply line 14 and sense ground line 15 are commonly provided to sense amplifiers arranged in sense amplifier arranging region (see FIG. 20). Therefore, sense power supply line 14 and sense ground line 15 should supply current stably in order to charge and discharge a large number of bit lines. When the sense amplifier circuit operates, many sense amplifiers SAs simultaneously operate to cause a large amount of bit line charging/discharging current to flow. If the voltage levels on sense power supply line 14 and sense ground line 15 vary due to the bit line charging/discharging current, a high speed sensing operation is impossible to delay the data access timing. Therefore, in order to supply current stably for charging and discharging of the bit lines in the sense operation, the resistance of sense supply line 14 and sense ground line 15 should be reduced as much as possible, and power supply voltage Vcc and ground voltage Vss should be stably kept.
However, if the widths of sense power supply line 14 and sense ground line 15 placed in sense amplifier arranging region 11 in FIG. 20 are increased, the area of sense amplifier arranging region 11 accordingly increases. The reason is that sense power supply line 14 and sense ground line 15 are formed at the first level aluminum interconnection layer as the conductive interconnection lines shown in FIG. 21. If sense power supply line 14 and sense ground line 15 are formed at a second level aluminum interconnection layer, confliction of interconnection lines occurs since a column selection line transmitting column selection signals YSa-YSm shown in FIG. 19A is also formed at the second level aluminum interconnection layer. Therefore, sense power supply line 14 and sense ground line 15 cannot be arranged at the second level aluminum interconnection layer.
The problem associated with the bit line equalize instruction signal also arises if the word lines have a word line shunt structure where a normal polysilicon word line and an interconnection line having a low resistance and located at an upper layer are electrically connected in a word line shunt region, instead of the hierarchical word line structure formed of the main word line/sub word line.